Regviz

Freescale Semiconductor /MK53DZ10 /I2S0 /IER

Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text

Interpret as IER

Share

Cut and paste this URL to share the unmodified register and value:

https://regviz.com/r/Freescale Semiconductor/MK53DZ10/I2S0/IER#0x0

31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (0)TFE0EN 0 (0)TFE1EN 0 (0)RFF0EN 0 (0)RFF1EN 0 (0)RLSEN 0 (0)TLSEN 0 (0)RFSEN 0 (0)TFSEN 0 (0)TUE0EN 0 (0)TUE1EN 0 (0)ROE0EN 0 (0)ROE1EN 0 (0)TDE0EN 0 (0)TDE1EN 0 (0)RDR0EN 0 (0)RDR1EN 0 (0)RXTEN 0 (0)CMDDUEN 0 (0)CMDAUEN 0 (0)TIE 0 (0)TDMAE 0 (0)RIE 0 (0)RDMAE 0 (0)TFRC_EN 0 (0)RFRC_EN

RDR1EN=0, CMDDUEN=0, TIE=0, TUE1EN=0, TLSEN=0, RLSEN=0, RFF0EN=0, TFE0EN=0, RFSEN=0, RXTEN=0, RFF1EN=0, TUE0EN=0, ROE0EN=0, RFRC_EN=0, RIE=0, CMDAUEN=0, TDE1EN=0, RDR0EN=0, TDE0EN=0, TFE1EN=0, TDMAE=0, TFSEN=0, ROE1EN=0, TFRC_EN=0, RDMAE=0

Description

I2S Interrupt Enable Register

Fields

TFE0EN

Enable Bit.

0 (0): Corresponding status bit cannot issue interrupt.

1 (1): Corresponding status bit can issue interrupt.
TFE1EN

Enable Bit.

0 (0): Corresponding status bit cannot issue interrupt.

1 (1): Corresponding status bit can issue interrupt.
RFF0EN

Enable Bit.

0 (0): Corresponding status bit cannot issue interrupt.

1 (1): Corresponding status bit can issue interrupt.
RFF1EN

Enable Bit.

0 (0): Corresponding status bit cannot issue interrupt.

1 (1): Corresponding status bit can issue interrupt.
RLSEN

Enable Bit.

0 (0): Corresponding status bit cannot issue interrupt.

1 (1): Corresponding status bit can issue interrupt.
TLSEN

Enable Bit.

0 (0): Corresponding status bit cannot issue interrupt.

1 (1): Corresponding status bit can issue interrupt.
RFSEN

Enable Bit.

0 (0): Corresponding status bit cannot issue interrupt.

1 (1): Corresponding status bit can issue interrupt.
TFSEN

Enable Bit.

0 (0): Corresponding status bit cannot issue interrupt.

1 (1): Corresponding status bit can issue interrupt.
TUE0EN

Enable Bit.

0 (0): Corresponding status bit cannot issue interrupt.

1 (1): Corresponding status bit can issue interrupt.
TUE1EN

Enable Bit.

0 (0): Corresponding status bit cannot issue interrupt.

1 (1): Corresponding status bit can issue interrupt.
ROE0EN

Enable Bit.

0 (0): Corresponding status bit cannot issue interrupt.

1 (1): Corresponding status bit can issue interrupt.
ROE1EN

Enable Bit.

0 (0): Corresponding status bit cannot issue interrupt.

1 (1): Corresponding status bit can issue interrupt.
TDE0EN

Enable Bit.

0 (0): Corresponding status bit cannot issue interrupt.

1 (1): Corresponding status bit can issue interrupt.
TDE1EN

Enable Bit.

0 (0): Corresponding status bit cannot issue interrupt.

1 (1): Corresponding status bit can issue interrupt.
RDR0EN

Enable Bit.

0 (0): Corresponding status bit cannot issue interrupt.

1 (1): Corresponding status bit can issue interrupt.
RDR1EN

Enable Bit.

0 (0): Corresponding status bit cannot issue interrupt.

1 (1): Corresponding status bit can issue interrupt.
RXTEN

Enable Bit.

0 (0): Corresponding status bit cannot issue interrupt.

1 (1): Corresponding status bit can issue interrupt.
CMDDUEN

Enable Bit.

0 (0): Corresponding status bit cannot issue interrupt.

1 (1): Corresponding status bit can issue interrupt.
CMDAUEN

Enable Bit.

0 (0): Corresponding status bit cannot issue interrupt.

1 (1): Corresponding status bit can issue interrupt.
TIE

Transmit Interrupt Enable.

0 (0): I2S transmitter interrupt requests disabled.

1 (1): I2S transmitter interrupt requests enabled.
TDMAE

Transmit DMA Enable.

0 (0): I2S transmitter DMA requests disabled.

1 (1): I2S transmitter DMA requests enabled.
RIE

Receive Interrupt Enable.

0 (0): I2S receiver interrupt requests disabled.

1 (1): I2S receiver interrupt requests enabled.
RDMAE

Receive DMA Enable.

0 (0): I2S receiver DMA requests disabled.

1 (1): I2S receiver DMA requests enabled.
TFRC_EN

Enable Bit.

0 (0): Corresponding status bit cannot issue interrupt.

1 (1): Corresponding status bit can issue interrupt.
RFRC_EN

Enable Bit.

0 (0): Corresponding status bit cannot issue interrupt.

1 (1): Corresponding status bit can issue interrupt.

Links

()

Register License

Redistribution and use in source and binary forms, with or without modification,\nare permitted provided that the following conditions are met:\n o Redistributions of source code must retain the above copyright notice, this list\n of conditions and the following disclaimer.\n o Redistributions in binary form must reproduce the above copyright notice, this\n list of conditions and the following disclaimer in the documentation and/or\n other materials provided with the distribution.\n o Neither the name of Freescale Semiconductor, Inc. nor the names of its\n contributors may be used to endorse or promote products derived from this\n software without specific prior written permission.\n THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS “AS IS” AND\n ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED\n WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE\n DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR\n ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES\n (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;\n LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON\n ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\n (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS\n SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.

 ()

Register Reference

https://github.com/cmsis-svd/cmsis-svd-data